1. Technical Field
This invention relates generally to transactions, such as memory requests and their responses, and more particularly to the conversion of such transactions into performable actions.
2. Description of the Prior Art
There are many different types of multi-processor computer systems. A symmetric multi-processor (SMP) system includes a number of processors that share a common memory. SMP systems provide scalability. As needs dictate, additional processors can be added. SMP systems usually range from two to 32 or more processors. One processor generally boots the system and loads the SMP operating system, which brings the other processors online. Without partitioning, there is only one instance of the operating system and one instance of the application in memory. The operating system uses the processors as a pool of processing resources, all executing simultaneously, where each processor either processes data or is in an idle loop waiting to perform a task. SMP systems increase in speed whenever processes can be overlapped.
A massively parallel processor (MPP) system can use thousands or more processors. MPP systems use a different programming paradigm than the more common SMP systems. In an MPP system, each processor contains its own memory and copy of the operating system and application. Each subsystem communicates with the others through a high-speed interconnect. To use an MPP system effectively, an information-processing problem should be breakable into pieces that can be solved simultaneously. For example, in scientific environments, certain simulations and mathematical problems can be split apart and each part processed at the same time.
A non-uniform memory access (NUMA) system is a multi-processing system in which memory is separated into distinct banks. NUMA systems are similar to SMP systems. In SMP systems, however, all processors access a common memory at the same speed. By comparison, in a NUMA system, memory on the same processor board, or in the same building block, as the processor is accessed faster than memory on other processor boards, or in other building blocks. That is, local memory is accessed faster than distant shared memory. NUMA systems generally scale better to higher numbers of processors than SMP systems.
Multi-processor systems usually include one or more memory controllers to manage memory transactions from the various processors. The memory controllers negotiate multiple read and write requests emanating from the processors, and also negotiate the responses back to these processors. Usually, a memory controller includes a pipeline, in which transactions, such as requests and responses, are input, and actions that can be performed relative to the memory for which the controller is responsible are output. The pipeline thus performs transaction conversion, converting the transactions to such actions that can be performed to effect the transactions. Transaction conversion is commonly performed in a single stage of a pipeline, such that transaction conversion to performable actions is performed in one step.
However, performing transaction conversion in a single stage of a pipeline suffers from some deficiencies. They may be inefficient, since the memory controller must convert a given transaction to performable actions before it acts on the next transaction. This can make the pipeline a bottleneck within the performance of the memory controller, decreasing overall performance of the memory controller, and hence the multi-processor system of which it is a part. Single-stage conversion may also be difficult to implement, due to the complexity involved in converting a transaction into performable actions.
Performing transaction conversion in multiple stages overcomes these problems. Such a solution is described in the commonly assigned patent application entitled “Multiple-Stage Pipeline for Transaction Conversion” Ser. No. 10/344,855. A given transaction is converted over a number of different stages. This enables more than one transaction to be processed at one time. For instance, a first stage may be processing one transaction, a second stage may be processing another transaction, and a third stage may be processing a third transaction, all at the same time.
A potential difficulty with converting transactions over a number of stages, where a number of transactions can be in the process of being converted all at the same time, is when two transactions are attempting to access the same memory line. For instance, one transaction may be attempting to write a value to the same memory line that another transaction is trying to read the value stored therein. This situation is generally known as a hazard. If hazards are not handled appropriately, they can cause processing errors within multi-processor systems, or, worse, may cause such systems to crash.
For these and other reasons, therefore, there is a need for the present invention.